/**
  ******************************************************************************
  * @file    psoc_dgc.h
  * @author  DGC
  * @version V1.0.0
  * @date    10:59 2013-10-2716:24 2016-6-29
  * @brief   This file contains all HW registers definitions and memory mapping.
  * 参考     cy8c4025库文件
  ******************************************************************************
 **/

 
 
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __PSOC4_DGC_H
#define __PSOC4_DGC_H

#define     __IO    volatile         /*!< defines 'read / write' permissions  */


typedef unsigned long _u8;
typedef unsigned short int  _u16;
typedef unsigned long _u32;



/******************************************************************************/
/*                          Peripherals Base Address                          */
/******************************************************************************/

#define GPIO0_BaseAddress       0x40040000u
#define GPIO1_BaseAddress       0x40040100u
#define GPIO2_BaseAddress       0x40040200u
#define GPIO3_BaseAddress       0x40040300u
#define GPIO4_BaseAddress       0x40040400u

typedef union
{
	volatile _u32  u32_data;
	struct
	{
		volatile _u8 BIT0     :1;                /* Bit 0  */
		volatile _u8 BIT1     :1;                /* Bit 1  */
		volatile _u8 BIT2     :1;                /* Bit 2  */
		volatile _u8 BIT3     :1;                /* Bit 3  */
		volatile _u8 BIT4     :1;                /* Bit 4  */
		volatile _u8 BIT5     :1;                /* Bit 5  */
		volatile _u8 BIT6     :1;                /* Bit 6  */
		volatile _u8 BIT7     :1;                /* Bit 7  */
		volatile _u8 BIT8     :1;                /* Bit 8  */
		volatile _u8 BIT9     :1;                /* Bit 9  */
		volatile _u8 BIT10    :1;                /* Bit 10 */
		volatile _u8 BIT11    :1;                /* Bit 11 */
		volatile _u8 BIT12    :1;                /* Bit 12 */
		volatile _u8 BIT13    :1;                /* Bit 13 */
		volatile _u8 BIT14    :1;                /* Bit 14 */
		volatile _u8 BIT15    :1;                /* Bit 15 */
		volatile _u8 BIT16    :1;                /* Bit 16 */
		volatile _u8 BIT17    :1;                /* Bit 17 */
		volatile _u8 BIT18    :1;                /* Bit 18 */
		volatile _u8 BIT19    :1;                /* Bit 19 */
		volatile _u8 BIT20    :1;                /* Bit 20 */
		volatile _u8 BIT21    :1;                /* Bit 21 */
		volatile _u8 BIT22    :1;                /* Bit 22 */
		volatile _u8 BIT23    :1;                /* Bit 23 */
		volatile _u8 BIT24    :1;                /* Bit 24 */
		volatile _u8 BIT25    :1;                /* Bit 25 */
		volatile _u8 BIT26    :1;                /* Bit 26 */
		volatile _u8 BIT27    :1;                /* Bit 27 */
		volatile _u8 BIT28    :1;                /* Bit 28 */
		volatile _u8 BIT29    :1;                /* Bit 29 */
		volatile _u8 BIT30    :1;                /* Bit 30 */
		volatile _u8 BIT31    :1;                /* Bit 31 */
	} Bits;
} _BitType;


//---------------------------------------------------------->>
//----------------          GPIO       --------------------->>
//---------------------------------------------------------->>

typedef struct GPIO_struct_dgc
{
	volatile _BitType DR; /*!< Output Data Register */
	volatile _BitType PS; /*!< Input Data Register */
} GPIO_TypeDef_DGC;

#define P0 ((GPIO_TypeDef_DGC *) GPIO0_BaseAddress)
#define P1 ((GPIO_TypeDef_DGC *) GPIO1_BaseAddress)
#define P2 ((GPIO_TypeDef_DGC *) GPIO2_BaseAddress)
#define P3 ((GPIO_TypeDef_DGC *) GPIO3_BaseAddress)
#define P4 ((GPIO_TypeDef_DGC *) GPIO4_BaseAddress)


#define P00_OUT (P0->DR).Bits.BIT0
#define P01_OUT (P0->DR).Bits.BIT1
#define P02_OUT (P0->DR).Bits.BIT2
#define P03_OUT (P0->DR).Bits.BIT3
#define P04_OUT (P0->DR).Bits.BIT4
#define P05_OUT (P0->DR).Bits.BIT5
#define P06_OUT (P0->DR).Bits.BIT6
#define P07_OUT (P0->DR).Bits.BIT7

#define P10_OUT (P1->DR).Bits.BIT0
#define P11_OUT (P1->DR).Bits.BIT1
#define P12_OUT (P1->DR).Bits.BIT2
#define P13_OUT (P1->DR).Bits.BIT3
#define P14_OUT (P1->DR).Bits.BIT4
#define P15_OUT (P1->DR).Bits.BIT5
#define P16_OUT (P1->DR).Bits.BIT6
#define P17_OUT (P1->DR).Bits.BIT7

#define P20_OUT (P2->DR).Bits.BIT0
#define P21_OUT (P2->DR).Bits.BIT1
#define P22_OUT (P2->DR).Bits.BIT2
#define P23_OUT (P2->DR).Bits.BIT3
#define P24_OUT (P2->DR).Bits.BIT4
#define P25_OUT (P2->DR).Bits.BIT5
#define P26_OUT (P2->DR).Bits.BIT6
#define P27_OUT (P2->DR).Bits.BIT7

#define P30_OUT (P3->DR).Bits.BIT0
#define P31_OUT (P3->DR).Bits.BIT1
#define P32_OUT (P3->DR).Bits.BIT2
#define P33_OUT (P3->DR).Bits.BIT3
#define P34_OUT (P3->DR).Bits.BIT4
#define P35_OUT (P3->DR).Bits.BIT5
#define P36_OUT (P3->DR).Bits.BIT6
#define P37_OUT (P3->DR).Bits.BIT7

#define P40_OUT (P4->DR).Bits.BIT0
#define P41_OUT (P4->DR).Bits.BIT1
#define P42_OUT (P4->DR).Bits.BIT2
#define P43_OUT (P4->DR).Bits.BIT3
#define P44_OUT (P4->DR).Bits.BIT4
#define P45_OUT (P4->DR).Bits.BIT5
#define P46_OUT (P4->DR).Bits.BIT6
#define P47_OUT (P4->DR).Bits.BIT7


#define P00_IN (P0->PS).Bits.BIT0
#define P01_IN (P0->PS).Bits.BIT1
#define P02_IN (P0->PS).Bits.BIT2
#define P03_IN (P0->PS).Bits.BIT3
#define P04_IN (P0->PS).Bits.BIT4
#define P05_IN (P0->PS).Bits.BIT5
#define P06_IN (P0->PS).Bits.BIT6
#define P07_IN (P0->PS).Bits.BIT7

#define P10_IN (P1->PS).Bits.BIT0
#define P11_IN (P1->PS).Bits.BIT1
#define P12_IN (P1->PS).Bits.BIT2
#define P13_IN (P1->PS).Bits.BIT3
#define P14_IN (P1->PS).Bits.BIT4
#define P15_IN (P1->PS).Bits.BIT5
#define P16_IN (P1->PS).Bits.BIT6
#define P17_IN (P1->PS).Bits.BIT7

#define P20_IN (P2->PS).Bits.BIT0
#define P21_IN (P2->PS).Bits.BIT1
#define P22_IN (P2->PS).Bits.BIT2
#define P23_IN (P2->PS).Bits.BIT3
#define P24_IN (P2->PS).Bits.BIT4
#define P25_IN (P2->PS).Bits.BIT5
#define P26_IN (P2->PS).Bits.BIT6
#define P27_IN (P2->PS).Bits.BIT7

#define P30_IN (P3->PS).Bits.BIT0
#define P31_IN (P3->PS).Bits.BIT1
#define P32_IN (P3->PS).Bits.BIT2
#define P33_IN (P3->PS).Bits.BIT3
#define P34_IN (P3->PS).Bits.BIT4
#define P35_IN (P3->PS).Bits.BIT5
#define P36_IN (P3->PS).Bits.BIT6
#define P37_IN (P3->PS).Bits.BIT7

#define P40_IN (P4->PS).Bits.BIT0
#define P41_IN (P4->PS).Bits.BIT1
#define P42_IN (P4->PS).Bits.BIT2
#define P43_IN (P4->PS).Bits.BIT3
#define P44_IN (P4->PS).Bits.BIT4
#define P45_IN (P4->PS).Bits.BIT5
#define P46_IN (P4->PS).Bits.BIT6
#define P47_IN (P4->PS).Bits.BIT7


// 
#define     SETBIT_0                0x01 
#define     SETBIT_1                0x02
#define     SETBIT_2                0x04 
#define     SETBIT_3                0x08
#define     SETBIT_4                0x10 
#define     SETBIT_5                0x20
#define     SETBIT_6                0x40 
#define     SETBIT_7                0x80

//
#define     CLRBIT_0                0x01 
#define     CLRBIT_1                0x02
#define     CLRBIT_2                0x04 
#define     CLRBIT_3                0x08
#define     CLRBIT_4                0x10 
#define     CLRBIT_5                0x20
#define     CLRBIT_6                0x40 
#define     CLRBIT_7                0x80


//P0
#define P00_0         (* (reg32 *) CYREG_GPIO_PRT0_DR_CLR) = CLRBIT_0
#define P00_1         (* (reg32 *) CYREG_GPIO_PRT0_DR_SET) = SETBIT_0

#define P01_0         (* (reg32 *) CYREG_GPIO_PRT0_DR_CLR) = CLRBIT_1
#define P01_1         (* (reg32 *) CYREG_GPIO_PRT0_DR_SET) = SETBIT_1

#define P02_0         (* (reg32 *) CYREG_GPIO_PRT0_DR_CLR) = CLRBIT_2
#define P02_1         (* (reg32 *) CYREG_GPIO_PRT0_DR_SET) = SETBIT_2

#define P03_0         (* (reg32 *) CYREG_GPIO_PRT0_DR_CLR) = CLRBIT_3
#define P03_1         (* (reg32 *) CYREG_GPIO_PRT0_DR_SET) = SETBIT_3

#define P04_0         (* (reg32 *) CYREG_GPIO_PRT0_DR_CLR) = CLRBIT_4
#define P04_1         (* (reg32 *) CYREG_GPIO_PRT0_DR_SET) = SETBIT_4

#define P05_0         (* (reg32 *) CYREG_GPIO_PRT0_DR_CLR) = CLRBIT_5
#define P05_1         (* (reg32 *) CYREG_GPIO_PRT0_DR_SET) = SETBIT_5

#define P06_0         (* (reg32 *) CYREG_GPIO_PRT0_DR_CLR) = CLRBIT_6
#define P06_1         (* (reg32 *) CYREG_GPIO_PRT0_DR_SET) = SETBIT_6

#define P07_0         (* (reg32 *) CYREG_GPIO_PRT0_DR_CLR) = CLRBIT_7
#define P07_1         (* (reg32 *) CYREG_GPIO_PRT0_DR_SET) = SETBIT_7


//P1
#define P10_0         (* (reg32 *) CYREG_GPIO_PRT1_DR_CLR) = CLRBIT_0
#define P10_1         (* (reg32 *) CYREG_GPIO_PRT1_DR_SET) = SETBIT_0

#define P11_0         (* (reg32 *) CYREG_GPIO_PRT1_DR_CLR) = CLRBIT_1
#define P11_1         (* (reg32 *) CYREG_GPIO_PRT1_DR_SET) = SETBIT_1

#define P12_0         (* (reg32 *) CYREG_GPIO_PRT1_DR_CLR) = CLRBIT_2
#define P12_1         (* (reg32 *) CYREG_GPIO_PRT1_DR_SET) = SETBIT_2

#define P13_0         (* (reg32 *) CYREG_GPIO_PRT1_DR_CLR) = CLRBIT_3
#define P13_1         (* (reg32 *) CYREG_GPIO_PRT1_DR_SET) = SETBIT_3

#define P14_0         (* (reg32 *) CYREG_GPIO_PRT1_DR_CLR) = CLRBIT_4
#define P14_1         (* (reg32 *) CYREG_GPIO_PRT1_DR_SET) = SETBIT_4

#define P15_0         (* (reg32 *) CYREG_GPIO_PRT1_DR_CLR) = CLRBIT_5
#define P15_1         (* (reg32 *) CYREG_GPIO_PRT1_DR_SET) = SETBIT_5

#define P16_0         (* (reg32 *) CYREG_GPIO_PRT1_DR_CLR) = CLRBIT_6
#define P16_1         (* (reg32 *) CYREG_GPIO_PRT1_DR_SET) = SETBIT_6

#define P17_0         (* (reg32 *) CYREG_GPIO_PRT1_DR_CLR) = CLRBIT_7
#define P17_1         (* (reg32 *) CYREG_GPIO_PRT1_DR_SET) = SETBIT_7

//P2
#define P20_0         (* (reg32 *) CYREG_GPIO_PRT2_DR_CLR) = CLRBIT_0
#define P20_1         (* (reg32 *) CYREG_GPIO_PRT2_DR_SET) = SETBIT_0

#define P21_0         (* (reg32 *) CYREG_GPIO_PRT2_DR_CLR) = CLRBIT_1
#define P21_1         (* (reg32 *) CYREG_GPIO_PRT2_DR_SET) = SETBIT_1

#define P22_0         (* (reg32 *) CYREG_GPIO_PRT2_DR_CLR) = CLRBIT_2
#define P22_1         (* (reg32 *) CYREG_GPIO_PRT2_DR_SET) = SETBIT_2

#define P23_0         (* (reg32 *) CYREG_GPIO_PRT2_DR_CLR) = CLRBIT_3
#define P23_1         (* (reg32 *) CYREG_GPIO_PRT2_DR_SET) = SETBIT_3

#define P24_0         (* (reg32 *) CYREG_GPIO_PRT2_DR_CLR) = CLRBIT_4
#define P24_1         (* (reg32 *) CYREG_GPIO_PRT2_DR_SET) = SETBIT_4

#define P25_0         (* (reg32 *) CYREG_GPIO_PRT2_DR_CLR) = CLRBIT_5
#define P25_1         (* (reg32 *) CYREG_GPIO_PRT2_DR_SET) = SETBIT_5

#define P26_0         (* (reg32 *) CYREG_GPIO_PRT2_DR_CLR) = CLRBIT_6
#define P26_1         (* (reg32 *) CYREG_GPIO_PRT2_DR_SET) = SETBIT_6

#define P27_0         (* (reg32 *) CYREG_GPIO_PRT2_DR_CLR) = CLRBIT_7
#define P27_1         (* (reg32 *) CYREG_GPIO_PRT2_DR_SET) = SETBIT_7

//P3
#define P30_0         (* (reg32 *) CYREG_GPIO_PRT3_DR_CLR) = CLRBIT_0
#define P30_1         (* (reg32 *) CYREG_GPIO_PRT3_DR_SET) = SETBIT_0

#define P31_0         (* (reg32 *) CYREG_GPIO_PRT3_DR_CLR) = CLRBIT_1
#define P31_1         (* (reg32 *) CYREG_GPIO_PRT3_DR_SET) = SETBIT_1

#define P32_0         (* (reg32 *) CYREG_GPIO_PRT3_DR_CLR) = CLRBIT_2
#define P32_1         (* (reg32 *) CYREG_GPIO_PRT3_DR_SET) = SETBIT_2

#define P33_0         (* (reg32 *) CYREG_GPIO_PRT3_DR_CLR) = CLRBIT_3
#define P33_1         (* (reg32 *) CYREG_GPIO_PRT3_DR_SET) = SETBIT_3

#define P34_0         (* (reg32 *) CYREG_GPIO_PRT3_DR_CLR) = CLRBIT_4
#define P34_1         (* (reg32 *) CYREG_GPIO_PRT3_DR_SET) = SETBIT_4

#define P35_0         (* (reg32 *) CYREG_GPIO_PRT3_DR_CLR) = CLRBIT_5
#define P35_1         (* (reg32 *) CYREG_GPIO_PRT3_DR_SET) = SETBIT_5

#define P36_0         (* (reg32 *) CYREG_GPIO_PRT3_DR_CLR) = CLRBIT_6
#define P36_1         (* (reg32 *) CYREG_GPIO_PRT3_DR_SET) = SETBIT_6

#define P37_0         (* (reg32 *) CYREG_GPIO_PRT3_DR_CLR) = CLRBIT_7
#define P37_1         (* (reg32 *) CYREG_GPIO_PRT3_DR_SET) = SETBIT_7

//P4
#define P40_0         (* (reg32 *) CYREG_GPIO_PRT4_DR_CLR) = CLRBIT_0
#define P40_1         (* (reg32 *) CYREG_GPIO_PRT4_DR_SET) = SETBIT_0

#define P41_0         (* (reg32 *) CYREG_GPIO_PRT4_DR_CLR) = CLRBIT_1
#define P41_1         (* (reg32 *) CYREG_GPIO_PRT4_DR_SET) = SETBIT_1

#define P42_0         (* (reg32 *) CYREG_GPIO_PRT4_DR_CLR) = CLRBIT_2
#define P42_1         (* (reg32 *) CYREG_GPIO_PRT4_DR_SET) = SETBIT_2

#define P43_0         (* (reg32 *) CYREG_GPIO_PRT4_DR_CLR) = CLRBIT_3
#define P43_1         (* (reg32 *) CYREG_GPIO_PRT4_DR_SET) = SETBIT_3

#define P44_0         (* (reg32 *) CYREG_GPIO_PRT4_DR_CLR) = CLRBIT_4
#define P44_1         (* (reg32 *) CYREG_GPIO_PRT4_DR_SET) = SETBIT_4

#define P45_0         (* (reg32 *) CYREG_GPIO_PRT4_DR_CLR) = CLRBIT_5
#define P45_1         (* (reg32 *) CYREG_GPIO_PRT4_DR_SET) = SETBIT_5

#define P46_0         (* (reg32 *) CYREG_GPIO_PRT4_DR_CLR) = CLRBIT_6
#define P46_1         (* (reg32 *) CYREG_GPIO_PRT4_DR_SET) = SETBIT_6

#define P47_0         (* (reg32 *) CYREG_GPIO_PRT4_DR_CLR) = CLRBIT_7
#define P47_1         (* (reg32 *) CYREG_GPIO_PRT4_DR_SET) = SETBIT_7


//(* (reg32 *) CYREG_GPIO_PRT1_DR_INV)  =0x02;


#define     INVBIT_0                0x01 
#define     INVBIT_1                0x02
#define     INVBIT_2                0x04 
#define     INVBIT_3                0x08
#define     INVBIT_4                0x10 
#define     INVBIT_5                0x20
#define     INVBIT_6                0x40 
#define     INVBIT_7                0x80


//P0  取反
#define     P00_INV       (* (reg32 *) CYREG_GPIO_PRT0_DR_INV) = INVBIT_0
#define     P01_INV       (* (reg32 *) CYREG_GPIO_PRT0_DR_INV) = INVBIT_1
#define     P02_INV       (* (reg32 *) CYREG_GPIO_PRT0_DR_INV) = INVBIT_2
#define     P03_INV       (* (reg32 *) CYREG_GPIO_PRT0_DR_INV) = INVBIT_3
#define     P04_INV       (* (reg32 *) CYREG_GPIO_PRT0_DR_INV) = INVBIT_4
#define     P05_INV       (* (reg32 *) CYREG_GPIO_PRT0_DR_INV) = INVBIT_5
#define     P06_INV       (* (reg32 *) CYREG_GPIO_PRT0_DR_INV) = INVBIT_6
#define     P07_INV       (* (reg32 *) CYREG_GPIO_PRT0_DR_INV) = INVBIT_7
//P1  取反
#define     P10_INV       (* (reg32 *) CYREG_GPIO_PRT1_DR_INV) = INVBIT_0
#define     P11_INV       (* (reg32 *) CYREG_GPIO_PRT1_DR_INV) = INVBIT_1
#define     P12_INV       (* (reg32 *) CYREG_GPIO_PRT1_DR_INV) = INVBIT_2
#define     P13_INV       (* (reg32 *) CYREG_GPIO_PRT1_DR_INV) = INVBIT_3
#define     P14_INV       (* (reg32 *) CYREG_GPIO_PRT1_DR_INV) = INVBIT_4
#define     P15_INV       (* (reg32 *) CYREG_GPIO_PRT1_DR_INV) = INVBIT_5
#define     P16_INV       (* (reg32 *) CYREG_GPIO_PRT1_DR_INV) = INVBIT_6
#define     P17_INV       (* (reg32 *) CYREG_GPIO_PRT1_DR_INV) = INVBIT_7

//P2  取反
#define     P20_INV       (* (reg32 *) CYREG_GPIO_PRT2_DR_INV) = INVBIT_0
#define     P21_INV       (* (reg32 *) CYREG_GPIO_PRT2_DR_INV) = INVBIT_1
#define     P22_INV       (* (reg32 *) CYREG_GPIO_PRT2_DR_INV) = INVBIT_2
#define     P23_INV       (* (reg32 *) CYREG_GPIO_PRT2_DR_INV) = INVBIT_3
#define     P24_INV       (* (reg32 *) CYREG_GPIO_PRT2_DR_INV) = INVBIT_4
#define     P25_INV       (* (reg32 *) CYREG_GPIO_PRT2_DR_INV) = INVBIT_5
#define     P26_INV       (* (reg32 *) CYREG_GPIO_PRT2_DR_INV) = INVBIT_6
#define     P27_INV       (* (reg32 *) CYREG_GPIO_PRT2_DR_INV) = INVBIT_7

//P3  取反
#define     P30_INV       (* (reg32 *) CYREG_GPIO_PRT3_DR_INV) = INVBIT_0
#define     P31_INV       (* (reg32 *) CYREG_GPIO_PRT3_DR_INV) = INVBIT_1
#define     P32_INV       (* (reg32 *) CYREG_GPIO_PRT3_DR_INV) = INVBIT_2
#define     P33_INV       (* (reg32 *) CYREG_GPIO_PRT3_DR_INV) = INVBIT_3
#define     P34_INV       (* (reg32 *) CYREG_GPIO_PRT3_DR_INV) = INVBIT_4
#define     P35_INV       (* (reg32 *) CYREG_GPIO_PRT3_DR_INV) = INVBIT_5
#define     P36_INV       (* (reg32 *) CYREG_GPIO_PRT3_DR_INV) = INVBIT_6
#define     P37_INV       (* (reg32 *) CYREG_GPIO_PRT3_DR_INV) = INVBIT_7

//P4  取反
#define     P40_INV       (* (reg32 *) CYREG_GPIO_PRT4_DR_INV) = INVBIT_0
#define     P41_INV       (* (reg32 *) CYREG_GPIO_PRT4_DR_INV) = INVBIT_1
#define     P42_INV       (* (reg32 *) CYREG_GPIO_PRT4_DR_INV) = INVBIT_2
#define     P43_INV       (* (reg32 *) CYREG_GPIO_PRT4_DR_INV) = INVBIT_3
#define     P44_INV       (* (reg32 *) CYREG_GPIO_PRT4_DR_INV) = INVBIT_4
#define     P45_INV       (* (reg32 *) CYREG_GPIO_PRT4_DR_INV) = INVBIT_5
#define     P46_INV       (* (reg32 *) CYREG_GPIO_PRT4_DR_INV) = INVBIT_6
#define     P47_INV       (* (reg32 *) CYREG_GPIO_PRT4_DR_INV) = INVBIT_7



#endif /* __CY8C4025_DGC_H */
